1. Field of the Invention
The present invention relates to a violation control circuit for a frame alignment of a basic interface in integrated services digital network (hereinafter referred to as ISDN).
2. Prior Art
In the basic interface in the ISDN, a frame alignment is established by detecting two times violations at a receiving side successively three times.
At the receiving side of a network termination (hereinafter referred to as NT) side, it is judged as a frame unalignment when the violation is not occured successively three times at the position where the frame unalignment bit is inserted.
At the receiving side of a terminal end (hereinafter referred to as TE) side, it is judged as a frame unalignment when the violation is not occured successively two times at the position where the frame alignment bit is inserted.
There is no concrete diagnosis for the frame alignment judging condition.
It is an object of the present invention to provide a violation control circuit in the ISDN capable of diagnosing the alignment guarding rule by preparing selector control signals for frame alignment, thereby generating a frame having the normal violation rule, enlarging or varying a violation generation range, or effecting the violation generation prohibition for unit frame so that the forward guarding stage and backward guarding stage of the frame alignment in the TE or a digital service unit (hereinafte referred to as DSU which corresponds to NT2). The forward guarding herein defines that when the number of occurences of the frame aligned state between the TE and the DSU exceeds a give" value (guarding stage), it is judged as unaligned state (hereinafter referred to as unalignment). The backward guarding defines that when the number of occurences of frames aligned state exceeds a give value (guarding stage), it is judged as an aligned state (hereinafter referred to as alignment).
To achieve the object of the present invention, the violation control circuit in the ISDN comprises a first selector having a first input connected to a negative polarity pulse transmission signal and a second input connected to a positive polarity pulse transmission signal, a second selector having a third input connected to the positive polarity pulse transmission signal and a fourth input connected to the negative polarity pulse transmission signal, a selector control circuit for providing a first control signal to connect the first input of the first selector to a first output of the first selector and connect the third input of the second selector to a second output of the second selector and providing a second control signal to connect the second input 1B of the first selector to the first output of the first selector and connect the fourth input of the second selector to the second output of the second selector, a unipolar-bipolar converter (U-B converter) for receiving the first output of the first selector and the second output of the second selector, a transmission transformer for receiving an output of the U-B converter, a receiving transformer for receiving a receiving pulse, a bipolar-unipolar converter (B-U converter) for receiving an output of the receiving transformer, and an INFO detecting circuit to be connected to an output of the B-U converter.